(a) Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same. More specifically, the present invention relates to a semiconductor device and a method of fabricating the same, involving a back grinding process for thinning a wafer in a wafer-level package in which a plurality of devices are formed.
It is noted that, in the description below, unless otherwise defined, a “semiconductor device” means an individual semiconductor element (device) which is formed in a wafer and which is still in an undivided state, as well as an individual semiconductor chip (device) after being divided from a wafer.
(b) Description of the Related Art
In recent years, with the demand for the miniaturization of electronic instruments and devices, attempts have been made to miniaturize and densify semiconductor devices used in the electronic instruments and devices. Accordingly, semiconductor devices each having a chip-scale package (CSP) structure in which miniaturization has been achieved by bringing the shape of a semiconductor device as close as possible to the shape of a semiconductor element (semiconductor chip), have been developed and fabricated.
In a typical semiconductor device having a CSP structure, a passivation film (insulating film) as a protective film is formed on the surface of a semiconductor wafer on the side where devices are formed, and a rerouting layer (rerouting pattern) for linking a wiring layer (electrode pads) of each device to the outside of a package through via holes formed in predetermined positions in the insulating film is formed on the insulating film. Further, metal posts are provided in terminal formation portions of the rerouting layer, and the entire surface on the side where the metal posts are formed is sealed with sealing resin (however, such that the tops of the metal posts are exposed). Furthermore, metal bumps as external connection terminals are bonded to the tops of the metal posts.
For various kinds of devices including flash memories, DRAMs, and the like, which are considered to be applications of semiconductor devices each having the above-described CSP structure, the future trend is that the demand for the thinning of wafer-level packages in a phase before they are divided into individual semiconductor chips is increasingly growing. In this connection, a process for grinding the backside of a wafer is generally performed to attempt the above-described thinning.
In a conventional fabrication process of a wafer-level package, a process for grinding the backside of a wafer has been performed in the initial phase. Namely, in a phase (phase before a passivation film (insulating film) is formed on a wafer surface) after a plurality of devices have been formed in a semiconductor wafer, the wafer has been thinned by a back grinding (BG) process using a wafer back grinding machine, which is a typical method, and then the wafer has been brought to the subsequent steps.
Technologies relating to the BG process for thinning a wafer as described above include, for example, one in which a wafer backside is ground after resin sealing, as described in Japanese unexamined Patent Publication (JPP) 2002-270720, or in JPP 2002-231854.
As described above, in a conventional fabrication process of a wafer-level package, a wafer back grinding process has been performed in the initial phase, and the wafer has needed to be brought to all the subsequent steps in a thinned state (thin-wafer state). Accordingly, there has been a high possibility in that a fatal defect called “wafer cracking” occurs during the fabrication process.
Further, there has also been a problem in that the entire wafer warps during the fabrication process where the wafer is thinned. For example, when sealing with mold resin and thermosetting (cure) thereof are performed, a very thin wafer is pulled toward the resin layer side under the influence of the thermal shrinkage of the mold resin, and thus the entire wafer warps. Accordingly, the wafer must be brought to the steps (solder ball placement, reflow, dicing, and the like) after the step of resin sealing in a warped state. Thus, in conventional technologies, there has been a disadvantage in that the entire wafer warps in thinning a wafer-level package.
One conceivable method for coping with such a disadvantage is, for example, to form a film layer (e.g., an interlayer insulating film for buildup, which is made of epoxy resin, silicone resin, polyimide resin, or the like) for warp correction on the wafer backside by vacuum lamination. In this case, an epoxy-based, silicone-based, polyimide-based film layer cannot be substantially stripped off after the film layer has been formed (after a cure process has been performed), and therefore needs to be left as a permanent film. Accordingly, various kinds of reliability tests including a test on the reliability of adhesiveness to the wafer need to be performed on the wafer having the permanent film (film layer for warp correction) attached thereto.
However, in this case, there is the following problem: when the wafer is finally diced and divided into individual semiconductor chips (devices), chipping, cracking, or the like, occur to each chip due to a mechanical shock during dicing, and the chipping or the like causes delamination between the permanent film (film layer) and the device interface (chip backside). Namely, since delamination occurs between the film layer and the chip backside after various kinds of reliability tests have been performed, the reliability tests performed once are wasted.
Moreover, in the above-described method in which a film-like epoxy resin material is formed for wafer warp correction, there is a disadvantage in that the number of steps is relatively large. Namely, such a film-like epoxy resin material typically has a two-layer structure in which a base material (PET film) made of polyester resin is coated with epoxy resin. In order to form such a film-like epoxy resin material on the wafer backside, the following four steps are needed: a step of laminating a film-like epoxy resin material on the wafer backside, a step of removing an unnecessary peripheral portion of the epoxy resin material, a step of stripping off a base material (PET film) protecting the epoxy resin, and a step of thermally curing the epoxy resin.
Furthermore, the film layer (insulating resin layer of epoxy resin or the like) formed on the wafer backside is left as a permanent film as it is even after dicing (after the wafer has been divided into chips). Accordingly, the backside of each chip (package) is covered with the insulating resin layer. This affects heat spread properties of the entire package.